Professor Sherief Reda's research group's paper titled Post-Silicon Power Characterization Using Thermal Infrared Emissions received the best paper award at the International Symposium on Low Power Electronics and Design (ISLPED). The paper is authored by Professor Reda, and Ph.D. students A. Nowroz and R. Cochran. This year ISLPED received 203 papers for evaluation. After the double-blind review process, 46 papers were accepted for full presentation. From the 46 papers, only 5 were nominated as best paper candidates, and finally only 2 papers were selected for the best paper awards. The competition was narrowed down between papers from Brown, Cornell, and RPI. The article is available at http://scale.engin.brown.edu/ pubs/islped10.pdf. The conference web page is http://www.islped.org
Showing posts with label reda. Show all posts
Showing posts with label reda. Show all posts
Monday, 23 August 2010
International Symposium on Low Power Electronics and Design awards Reda's group with best paper
Posted on 08:51 by Unknown
Tuesday, 17 August 2010
A. Richard Newton Graduate Scholarship awarded to Cochran and Nowroz
Posted on 09:24 by Unknown
Pictured left to right: Cochran, DAC Official, Reda, and Nowroz
2010 Recipients
Students: Ryan J. Cochran, Abdullah N. Nowroz - Brown Univ., Providence, RI
Project: Adaptive Hot Spot Cooling for Many-Core Processors
Advisor: Sherief Reda – Brown Univ., Providence, RI
Biography information:
Ryan J. Cochran first came to Brown University from West Chester, PA as an undergraduate student in engineering, and graduated with Honors in the spring of 2008 in Electrical Engineering. He returned to Brown as a M.Sc. student in the fall of 2008, but has since decided to continue his studies as a Ph.D. student in Electrical Engineering at Brown. Ryan's principal research areas include thermal modeling, management, and tool development for current and future nano-scale integrated circuit technologies. Since 2009, Ryan has 4 refereed conference papers in his research area, including a best paper nomination in ISLPED 2010.
Abdullah Nazma Nowroz was born in Newcastle Upon Tyne, United Kingdom and grew up in Bangladesh. She graduated Summa Cum Laude in Electrical Engineering from Boston University in 2006. In 2007, she decided to come back to academia after working in Bangladesh for one year and completed her Masters in Electrical Engineering VLSI from University of Southern California. At present, she is working in the SCALE lab, where she works on designing many innovative techniques towards effective management of temperature, power, and performance of many-core processors. Projects include devising thermal sensor allocation techniques and signal reconstruction techniques that fully characterize the thermal status of the processor using limited number of measurements from the thermal sensors. Her research also includes techniques that provide detailed post-silicon power characterization using thermal emissions from the backside of silicon die using state-of-the-art infrared camera.
Wednesday, 17 February 2010
NSF Career Awards to Dworak and Reda
Posted on 10:34 by Unknown
Two young faculty members in the Division join the ranks of our faculty that have been awarded the NSF CAREER Awards, Jennifer Dworak and Sherief Reda. The Faculty Early Career Development (CAREER) Program is a Foundation-wide activity that offers the National Science Foundation's most prestigious awards in support of the early career-development activities of those teacher-scholars who most effectively integrate research and education within the context of the mission of their organization.
Enhancing Quality through Probabilistic On-Chip Test
Jennifer Dworak
Future integrated circuits will contain tens, hundreds, or possibly even a thousand cores per chip. However, the scaling techniques that will make this possible also make the underlying circuit fabric less reliable—leading to increased wearout and defects that cannot be detected at manufacturing. In response, the PI proposes fundamental research for generating new test sets on-chip to identify failing cores. The tests will be created “on-the-fly” and dynamically targeted to the most critical areas of a core. Some key portions of the proposed research involve the creation and verification of hardware monitors for determining which faults are most important for the user’s applications, the diagnostic use of online error detection hardware to pinpoint locations that caused previous failures, and the analysis and development of protocols to efficiently create and transport tests in a network-on-chip environment.
The great performance advantages of future multi-core devices will remain unrealized if the reliability of those devices cannot be trusted. The proposed research investigates critical tools for promoting that reliability. The integrated education plan provides research opportunities for students at multiple levels—from high school to graduate school—including students from underrepresented groups. In addition to recruiting undergraduates from Brown, the PI plans to work with the CRA-W DREU (Distributed Research Experiences for Undergraduates) program to host visiting female undergraduates for summer research. The PI will also recruit high school students from the Providence Public Schools, many of whom are members of underrepresented groups, for summer research through the Brown GK-12 program.
Link: http://www.nsf.gov/awardsearch/showAward.do?AwardNumber=0915302
Elevated temperature is a major problem for the reliability, performance, power consumption, and packaging costs of integrated electronic devices.
Enhancing Quality through Probabilistic On-Chip Test
Jennifer Dworak
Future integrated circuits will contain tens, hundreds, or possibly even a thousand cores per chip. However, the scaling techniques that will make this possible also make the underlying circuit fabric less reliable—leading to increased wearout and defects that cannot be detected at manufacturing. In response, the PI proposes fundamental research for generating new test sets on-chip to identify failing cores. The tests will be created “on-the-fly” and dynamically targeted to the most critical areas of a core. Some key portions of the proposed research involve the creation and verification of hardware monitors for determining which faults are most important for the user’s applications, the diagnostic use of online error detection hardware to pinpoint locations that caused previous failures, and the analysis and development of protocols to efficiently create and transport tests in a network-on-chip environment.
The great performance advantages of future multi-core devices will remain unrealized if the reliability of those devices cannot be trusted. The proposed research investigates critical tools for promoting that reliability. The integrated education plan provides research opportunities for students at multiple levels—from high school to graduate school—including students from underrepresented groups. In addition to recruiting undergraduates from Brown, the PI plans to work with the CRA-W DREU (Distributed Research Experiences for Undergraduates) program to host visiting female undergraduates for summer research. The PI will also recruit high school students from the Providence Public Schools, many of whom are members of underrepresented groups, for summer research through the Brown GK-12 program.
Link: http://www.nsf.gov/awardsearch/showAward.do?AwardNumber=0915302
Transcending the Thermal Management Challenges of Tera-Scale Computing
Sherief Reda
Elevated temperature is a major problem for the reliability, performance, power consumption, and packaging costs of integrated electronic devices.Temperature is a main physical barrier limiting the performance benefits of future technologies that promise tera-scale integration. To meet the thermal management challenges of future many-core processors, this research program envisions a new class of intelligent dynamic thermal management systems that explore the vast search space of possible control parameter settings and decide the optimal temperature and performance targets. This research program also investigates new cooling system designs that enable the thermal management system to target directly hot spots at the micro scale. Directly targeting hot spots alleviates the thermal constraints on performance.
The proposed research program will lead to transformative solutions and tools that address the fundamental thermal management challenges of computing systems and ensure their scalability. The proposed program will lead to the training of a diverse workforce of undergraduate and graduate students to be well prepared to deal with tomorrow’s thermal management challenges. The educational component of this program includes (1) research experiences for undergraduates; (2) integrated approach to entrepreneurship education with research; (3) hands-on training through the development of educational laboratories based on a state-of-the-art infrared camera; and (4) continuous education through the development of high-quality educational materials and an interactive technical Web site.
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